Verilog simulation and synthesis tool. #Verilog simulator #Verilog compiler #Verilog synthesis #Simulate #Compile #Verilog
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format.
For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlists in the desired format.
The compiler proper is intended to elaborate and parse design descriptions written to the IEEE standard IEEE Std 1364-2001. The standard proper was released towards the middle of the year 2001, though in a rather pricey electronic form.
This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal.
NOTE: Icarus Verilog is a work in progress, and since the language standard is not standing still either, it probably always will be.
Icarus Verilog 10.0
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- Mac OS X (-)
- file size:
- 1.7 MB
- main category:
- Math/Scientific
- developer:
- visit homepage
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- Windows Sandbox Launcher
- Bitdefender Antivirus Free
- Context Menu Manager
- Microsoft Teams
- IrfanView
- Zoom Client
- 7-Zip
- ShareX
- 4k Video Downloader