What's new in Icarus Verilog 0.9.4
Mar 18, 2011
- Language Coverage Edit:
- Add support for using the &&, || and ! operators with real constant values.
- Add support for passing -0.0 from the compiler to the run time.
- Add support for parsing pull devices that have two strengths specified.
- Allow multiple attribute instances.
- Language Extensions Edit:
- General Bug Fixes Edit:
- Fix a bug when using the === and !== operators with signed values.
- Skip NULL system task/function arguments when performing @* processing.
- Fix some bugs related to tasks with integer/real arguments.
- Fix a bug in the normalization of part selects.
- Fix some bugs in the compiler shift code.
- A port driven by a constant should not be coerced to inout.
- Fix the display of strings with the MSB set or with embedded NULLs.
- When padding a string keep the string property if the padding is a multiple of eight.
- Add a check for incorrectly creating a vector of reals vs an array of reals.
- Some minor SDF support improvements, but development has much better SDF support.
- Add a warning that Icarus does not support the Cadence style of ifnone.
- Correctly calculate the width of a signed constant.
- Update the FST dumper files to the latest from GTKWave.
- Improve some of the error/warning messages.
- Numerous other bug fixes (the complete details can be found in the commit logs for the v0_9-branch of iverilog on github).
- Things That Still Don't Work Edit
- This isn't necessarily a complete list of missing features, but this should at least list the missing features that you are likely to encounter.
- Missing Language Features Edit
- PLA modeling system tasks.
- Stochastic analysis system tasks.
- Multi-dimensional arrays.
- Timing checks (they are currently ignored).
- The various pulse limits/controls.
- specparam with a range, outside a specify block, back-annotation, or referencing another specparam.
- Constant user functions.
- Net delays.
- trireg nets (capacitive networks).
- Inertial delays from the PLI
- Bugs fixed/enhancements in development that will not be added to V0.9 Edit
- The way VVP handles nets has been reworked. This allows force, etc. to work correctly.
- Reworked the initial value propagation and make the value more standard.
- A uwire with multiple drivers will now be reported as an error during code generation.
- Added better support for SDF back annotation and delay selection.
- Added delay support to tranif gates and other improvements.
- Added support for two variable delays where appropriate.
- Added support for a UDP with a variable delay.
- Added support for overriding a parameter from the command line/command file.
- Better/more efficient support of signed or undefined variable selects.
- Added non-blocking assignment to a real array.
- Add full support for SystemVerilog $fatal, $error, $warning and $info.
- Add basic support for SystemVerilog two value variables.
- Added SystemVerilog timeunit and timeprecision.
- Added all the Verilog-AMS and SystemVerilog keywords when appropriate.
- A number of VHDL target fixes.
- Added support for `celldefine and vpiCellInstance.
- Added support for vpiUserSystf iteration, vpi_get_systf_info(), etc.
- Reworked how parameter expressions are processed.
- Rework how the expression width/type is calculated.
- Add support for reading VHDL files (ongoing).
- Add target for generating 1364-1995 compatible code (ongoing).
- Add __FILE__ and __LINE__ macros (with limitations).
- Add a compilation option that instruments the vvp code to allow run time statement tracing.
- Some general speedup improvements.
- Various compilation and warning fixes/updates.
- A number of other bug fixes.