What's new in Verilog Tool Framework 1.0.110
Sep 7, 2015
- Fixed issues with interface and variable namespace collisions
- Fixed issues with interface and port namespace collisions
- Fixed parsing issues with non-ansi interface port declarations
- Enable parameter and localparam to be used inside interface definitions
- Fixed issues with interface definition and interface instance namespace collisions
- Allow 'none' to be used as argument to `default_nettype
- Fixed preprocessor bug with macro arguments partially matching
New in Verilog Tool Framework 1.0.109 (Aug 10, 2015)
- Allow interface instance names to be the same as the interface name
- Fixed type resolution for interface members. Manifested itself as errors when xproping ternary operations
New in Verilog Tool Framework 1.0.104 (Apr 29, 2015)
- Added support for modports
- Fixed bug with genvar declaration in for construct
- Bumped rev to 1.0.104
New in Verilog Tool Framework 1.0.103 (Mar 24, 2015)
- Added support for trailing labels on named begin/end blocks, fork/join, package/endpackage
- Added support for interfaces
- Bumped rev to 1.0.103
New in Verilog Tool Framework 1.0.102 (Nov 4, 2014)
- Fixed bug in sim tool that caused hangs due to constant expression optimization
- Enhanced log and key file handling in sim plugin
New in Verilog Tool Framework 1.0.101 (Aug 25, 2014)
- Fix warning with gcc-4.8.2
- Updates to make cygwin compile work (all plugins are statically compiled in)
New in Verilog Tool Framework 1.0.97 (Jul 22, 2013)
- Fixed segfault when compiled with gcc 4.7.2
- Cleaned up warnings when compiled with gcc 4.7.2
- Remove extra whitespace inserted after `define statements when keeptickdefine switch is used
New in Verilog Tool Framework 1.0.96 (Jun 29, 2012)
- sim tool: fixed dumpvar bug that cause timestamps to not be emitted
- Added support for null named parameter args
- Added support for wildcard port connections
- Fixed bug that cause assertions with inline function calls between port list and port definitions.
New in Verilog Tool Framework 1.0.94 (Apr 17, 2012)
- Disable instrumentation of casex expression and case
New in Verilog Tool Framework 1.0.93 (Feb 13, 2012)
- adding $signed width and type attribute calculation
New in Verilog Tool Framework 1.0.92 (Feb 10, 2012)
- rectify tool: x rectification is now done on a bit by bit basis.
- xprop tool: create signed constants in xprop signed expressions.
- Fixed bug with enum values not being allow in param/localparam statements
New in Verilog Tool Framework 1.0.91 (Oct 14, 2011)
- Enabled pragmas to occur at statement boundries in generate blocks.
New in Verilog Tool Framework 1.0.90 (Oct 6, 2011)
- Fixed bug with symbolic width expression dependent upon volatile expressions. Changed code to not resolve parameters.
New in Verilog Tool Framework 1.0.89 (Sep 15, 2011)
- Fixed parser to allow begin/end pair in module level generate
- statements
- xprop tool: Restructure pragma insertion on instrumented code to better work with coverage tools
New in Verilog Tool Framework 1.0.88 (Jul 27, 2011)
- Enhance error reporting for undefined references at global scope.
- xprop tool: Fixed bug with +dump-fcc switch that incorrectly parsed
- comments when converting them.
- dump tool: Added +dump-alt-rxnor switch to dump '^~' instead of `~^'
New in Verilog Tool Framework 1.0.87 (Jul 14, 2011)
- Change flatten tool to not require all instances to be resolved.
- Policy of message flatten-MISUD is by default warning so a warning
- message is printed for all unresolved modules.
New in Verilog Tool Framework 1.0.86 (Jul 1, 2011)
- Fixed bug that ignored a reg declaration before an output declaration in a module definitions.
- This caused the parser to accept illegal verilog which in turn cause the xprop filter to take a segmentation violation.
New in Verilog Tool Framework 1.0.82 (Dec 6, 2010)
- xprop: Fixed segfault that happens during clock xprop due
- to improperly declared variable.
- xprop: Fixed non-linear behavior with xprop on deep nested '?'
- operators that results long execution time and high memory usage.
- xprop: Fixed segfault caused by procedural assignment to
- net. This really should be caught in the parsing phase.
New in Verilog Tool Framework 1.0.81 (Oct 11, 2010)
- Fixed segfault cause by functions declared outside module declarations.
New in Verilog Tool Framework 1.0.80 (Sep 10, 2010)
- xprop: Fixed seqmentation fault when complex types with a terminating part select (+: or -:) are xprop'd.
- Bumped rev to 1.0.80
New in Verilog Tool Framework 1.0.79 (Sep 7, 2010)
- Added support for unbased unsigned literals.
- Added support for c style dimensions in unpacked dimension declarations.
New in Verilog Tool Framework 1.0.78 (Sep 1, 2010)
- Fixed bug in width determination of bit selects. This bug was
- causing xprop error messages (where there should have been none)
- for xprop of the ternary operator.
- Bumped rev to 1.0.78.
New in Verilog Tool Framework 1.0.77 (Jul 19, 2010)
- xprop: Fixed latch xpropagation seg faults
- xprop: Fixed clock prop on registers with this form:
- always @(posedge clk or negedge rst)
- if( !rst ) ...
- else ...
- Added support for wire defintions outside of modules
- Bumped rev to 10.0.77
New in Verilog Tool Framework 1.0.76 (Jun 8, 2010)
- Cleaning up internal structure in preparation for xproping structs
- and packed arrays.
- remove +dump-disable-select and +dump-disable-array switches
- added +dump-disable-index switch
- Added return statement.
- Added trailing function/task labels
- Added ++ -- support
- Added '' '" '\'" preprocessor directives
- Added always_comb, always_ff, always_latch
- Added complex function return types
- Added unpacked function/task/module args
- Added sv style for/generate constructs
- Added cast operators
- Added +=,-=,*=,/=.%=,&=,|=,^=,=,= assignment ops
- Added directionless function port support.
- Bumped rev to 10.0.76
New in Verilog Tool Framework 1.0.75 (May 6, 2010)
- Adding packed dimensions to parser.
- Added typedefs, structs, and enums to parser.
- xprop: disabled support for xprop on blocking assignments with delay
- specifications. Added error message for this case.
New in Verilog Tool Framework 1.0.74 (Apr 22, 2010)
- Allow continuous assigns to variables when -sv switch is enabled.
- Remove restriction of 256 characters on file pathnames.
- Bumped rev to 10.0.74
New in Verilog Tool Framework 1.0.67 (Dec 21, 2009)
- Fixed initialization bug that causes test suite to fail on
- 32 bit OS with gcc 4.4.2.
- Bumped rev to 1.0.67
New in Verilog Tool Framework 1.0.47 (Mar 23, 2009)
- Fixed bug which causes passthru pragmas to not be ignored in disabled regions of code bounded with `ifdef/`ifndef/`endif.
New in Verilog Tool Framework 1.0.46 (Mar 12, 2009)
- Added begin/end comments around 'if' in clock instrumentation.
New in Verilog Tool Framework 1.0.45 (Mar 10, 2009)
- Fixed output bug which caused n-(-m) to be converted to n--m.
New in Verilog Tool Framework 1.0.44 (Mar 6, 2009)
- Fixed bug with `define resolution within comments that messes up when carriage returns are embedded.
New in Verilog Tool Framework 1.0.43 (Feb 16, 2009)
- initial conversion to automake/autoconf
New in Verilog Tool Framework 1.0.42 (Feb 5, 2009)
- When detemining expressions for widths use ? operator to figure out range direction when arguments are volatile.
- Replace newlines with space in macro inserted in comments
New in Verilog Tool Framework 1.0.41 (Jan 29, 2009)
- treat real variables as non-x
- don't instrument ? operator if condition cannot be x or expression is real.
New in Verilog Tool Framework 1.0.40 (Jan 26, 2009)
- xprop tool changed to not xprop on real expressions
- Allow real and realtime function arguments
- Fixed parser bug with constant functions
- Removed code that was restricting comment placement in port lists
New in Verilog Tool Framework 1.0.39 (Jan 12, 2009)
- Fixed dumpvars bug which omitted first timestamp in output file
- Fixed xprop tool to properly handle partial index array assignments
- Added support for '**' operator
New in Verilog Tool Framework 1.0.38 (Jan 6, 2009)
- Added new backend api routine to cause lexer to ignore vrq translate on/off pragmas for sim plugin
- Enhanced module search function to find modules pulled in by other module searches.
- fixed timescale processing for modules that are loaded via library search
- fixed parsing of 'dx and 'dz * add optimizations to sim tool
New in Verilog Tool Framework 1.0.36 (Nov 14, 2008)
- Change format for output case items. Each item is now on a seperate line.