Verilog Tool Framework 1.0.94 - Changelog

What's new in Verilog Tool Framework 1.0.94:

April 17th, 2012

· Disable instrumentation of casex expression and case

What's new in Verilog Tool Framework 1.0.93:

February 13th, 2012

· adding $signed width and type attribute calculation

What's new in Verilog Tool Framework 1.0.92:

February 10th, 2012

· rectify tool: x rectification is now done on a bit by bit basis.
· xprop tool: create signed constants in xprop signed expressions.
· Fixed bug with enum values not being allow in param/localparam statements

What's new in Verilog Tool Framework 1.0.91:

October 14th, 2011

· Enabled pragmas to occur at statement boundries in generate blocks.

What's new in Verilog Tool Framework 1.0.90:

October 6th, 2011

· Fixed bug with symbolic width expression dependent upon volatile expressions. Changed code to not resolve parameters.

What's new in Verilog Tool Framework 1.0.89:

September 15th, 2011

· Fixed parser to allow begin/end pair in module level generate
· statements
· xprop tool: Restructure pragma insertion on instrumented code to better work with coverage tools

What's new in Verilog Tool Framework 1.0.88:

July 27th, 2011

· Enhance error reporting for undefined references at global scope.
· xprop tool: Fixed bug with +dump-fcc switch that incorrectly parsed
· comments when converting them.
· dump tool: Added +dump-alt-rxnor switch to dump '^~' instead of `~^'

What's new in Verilog Tool Framework 1.0.87:

July 14th, 2011

· Change flatten tool to not require all instances to be resolved.
· Policy of message flatten-MISUD is by default warning so a warning
· message is printed for all unresolved modules.

What's new in Verilog Tool Framework 1.0.86:

July 1st, 2011

· Fixed bug that ignored a reg declaration before an output declaration in a module definitions.
· This caused the parser to accept illegal verilog which in turn cause the xprop filter to take a segmentation violation.

What's new in Verilog Tool Framework 1.0.82:

December 6th, 2010

· xprop: Fixed segfault that happens during clock xprop due
· to improperly declared variable.
· xprop: Fixed non-linear behavior with xprop on deep nested '?'
· operators that results long execution time and high memory usage.
· xprop: Fixed segfault caused by procedural assignment to
· net. This really should be caught in the parsing phase.

What's new in Verilog Tool Framework 1.0.81:

October 11th, 2010

· Fixed segfault cause by functions declared outside module declarations.

What's new in Verilog Tool Framework 1.0.80:

September 10th, 2010

· xprop: Fixed seqmentation fault when complex types with a terminating part select (+: or -:) are xprop'd.
· Bumped rev to 1.0.80

What's new in Verilog Tool Framework 1.0.79:

September 7th, 2010

· Added support for unbased unsigned literals.
· Added support for c style dimensions in unpacked dimension declarations.

What's new in Verilog Tool Framework 1.0.78:

September 1st, 2010

· Fixed bug in width determination of bit selects. This bug was
· causing xprop error messages (where there should have been none)
· for xprop of the ternary operator.
· Bumped rev to 1.0.78.

What's new in Verilog Tool Framework 1.0.77:

July 19th, 2010

· xprop: Fixed latch xpropagation seg faults
xprop: Fixed clock prop on registers with this form:
· always @(posedge clk or negedge rst)
· if( !rst ) ...
· else ...
· Added support for wire defintions outside of modules
· Bumped rev to 10.0.77

What's new in Verilog Tool Framework 1.0.76:

June 8th, 2010

· Cleaning up internal structure in preparation for xproping structs
· and packed arrays.
· remove +dump-disable-select and +dump-disable-array switches
· added +dump-disable-index switch
· Added return statement.
· Added trailing function/task labels
· Added ++ -- support
· Added '' '" '\'" preprocessor directives
· Added always_comb, always_ff, always_latch
· Added complex function return types
· Added unpacked function/task/module args
· Added sv style for/generate constructs
· Added cast operators
· Added +=,-=,*=,/=.%=,&=,|=,^=,=,= assignment ops
· Added directionless function port support.
· Bumped rev to 10.0.76

What's new in Verilog Tool Framework 1.0.75:

May 6th, 2010

· Adding packed dimensions to parser.
· Added typedefs, structs, and enums to parser.
· xprop: disabled support for xprop on blocking assignments with delay
· specifications. Added error message for this case.

What's new in Verilog Tool Framework 1.0.74:

April 22nd, 2010

· Allow continuous assigns to variables when -sv switch is enabled.
· Remove restriction of 256 characters on file pathnames.
· Bumped rev to 10.0.74

What's new in Verilog Tool Framework 1.0.67:

December 21st, 2009

· Fixed initialization bug that causes test suite to fail on
· 32 bit OS with gcc 4.4.2.
· Bumped rev to 1.0.67

What's new in Verilog Tool Framework 1.0.47:

March 23rd, 2009

· Fixed bug which causes passthru pragmas to not be ignored in disabled regions of code bounded with `ifdef/`ifndef/`endif.

What's new in Verilog Tool Framework 1.0.46:

March 12th, 2009

· Added begin/end comments around 'if' in clock instrumentation.

What's new in Verilog Tool Framework 1.0.45:

March 10th, 2009

· Fixed output bug which caused n-(-m) to be converted to n--m.

What's new in Verilog Tool Framework 1.0.44:

March 6th, 2009

· Fixed bug with `define resolution within comments that messes up when carriage returns are embedded.

What's new in Verilog Tool Framework 1.0.43:

February 16th, 2009

· initial conversion to automake/autoconf

What's new in Verilog Tool Framework 1.0.42:

February 5th, 2009

· When detemining expressions for widths use ? operator to figure out range direction when arguments are volatile.
· Replace newlines with space in macro inserted in comments

What's new in Verilog Tool Framework 1.0.41:

January 29th, 2009

· treat real variables as non-x
· don't instrument ? operator if condition cannot be x or expression is real.

What's new in Verilog Tool Framework 1.0.40:

January 26th, 2009

· xprop tool changed to not xprop on real expressions
· Allow real and realtime function arguments
· Fixed parser bug with constant functions
· Removed code that was restricting comment placement in port lists

What's new in Verilog Tool Framework 1.0.39:

January 12th, 2009

· Fixed dumpvars bug which omitted first timestamp in output file
· Fixed xprop tool to properly handle partial index array assignments
· Added support for '**' operator

What's new in Verilog Tool Framework 1.0.38:

January 6th, 2009

· Added new backend api routine to cause lexer to ignore vrq translate on/off pragmas for sim plugin
· Enhanced module search function to find modules pulled in by other module searches.
· fixed timescale processing for modules that are loaded via library search
· fixed parsing of 'dx and 'dz * add optimizations to sim tool

What's new in Verilog Tool Framework 1.0.36:

November 14th, 2008

· Change format for output case items. Each item is now on a seperate line.