Java tool to find the dependency of VHDL/Verilog files
sorthdl takes all the RTL files as input and then process those files internally and come up with a sorted/ordered list of files along with their proper VHDL /Verilog work library.
sorthdl takes a input file which contains all the Verilog and/or VHDL files(one file per line without any * or regular expression in the file name ).
You can simply redirect the output of the 'ls' command to create this file. Make sure that there is no special character e.g. '*' or '@' in the name of files. After processing all the listed files it will finally create a modelsim compilation script named 'modelsim_compile.csh'.